|Institution:||University of Washington|
|Full text PDF:||http://hdl.handle.net/1773/5999|
This dissertation presents an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model is used in a new version of a gate-sizing tool called Forge, which not only exhibits optimality, but also efficiently produces the area versus delay trade-off curve for a combinational logic block in one step. Forge includes a realistic delay propagation scheme that combines arrival times and slew-rates. The gate delay model is within 1% of Hspice, on average, and the computed worst-case path delays are with 2% of Hspice, on average. Forge is 9X faster than a leading commercial transistor sizing tool, while achieving better delay targets and uses 29% less transistor area for specific delay targets, on average.