|Institution:||Universidade do Porto|
|Keywords:||Engenharia electrotécnica; electrónica e informática|
|Full text PDF:||http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/85147|
In this dissertation we propose to develop, implement, and validate a software based clock synchronization algorithm in a many-core processor architecture, specifically the Kalray MPPA-256 architecture. This work was the objective of reducing the effect of clock skew in many-core architectures, so that we can take full advantage of this hardware type in real-time applications. Advisors/Committee Members: Faculdade de Engenharia.