Abstracts Computer Science

Architectural support for multithreading on a 4-way multiprocessor

by Gwang-Myung Kim

The microprocessors will have more than a billion logic transistors on a single chip in the near future. Several alternatives have been suggested for obtaining highest performance with billion-transistor chips. To achieve the highest performance possible, an on-chip multiprocessor will become one promising alternative to the current superscalar microprocessor. It may execute multiple threads effectively on multiple processors in parallel if the application program is parallelized properly. This increases the utilization of the processor and provides latency tolerance for the latency caused from data dependency and cache misses. The Electronics and Telecommunications Research Institute (ETRI) in South Korea developed an on-chip multiprocessor RAPTOR Simulator "RapSim", which contains four SPARC microprocessor cores in it. To support this 4-way multiprocessor simulator, Multithreaded Mini Operating System (MMOS) was developed by OSU MMOS group. RapSim runs multiple threads on multiple processor cores concurrently. POSIX threads was used to build Symmetric Multiprocessor (SMP) safe Pthreads package, called MMOS. Benchmarks should be properly parallelized by the programmer to run multiple threads across the multiple processors simultaneously. Performance simulation results shows the RAPTOR can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multiprocessor designs.